1. Field of the Invention
The present invention relates to semiconductor integrated circuits which are of high reliability and high packing density and permits a multilayer construction. The invention also pertains to a manufacturing process of such semiconductor integrated circuits.
2. Description of the Prior Art
In recent years, semiconductor integrated circuit technology has achieved a remarkable development for high packing density and high operating speed. Especially, marked innovations have been made in the fabrication technology; for instance, new lithographic techniques such as electron-beam lithography, projection photolithography and X-ray lithography have been introduced, and etching techniques suitable for microfabrication of semiconductor integrated circuits, such as parallel plate plasma etching, have also been introduced. The abovesaid new lithographic techniques permit the formation of a submicron resist pattern, and the dry etching technology enables anisotropic etching and possesses the advantage that it is able to perform satisfactory etching of a submicron pattern without incurring undercutting. Now that such miniature patterning technology and anisotropic etching technology have been introduced into the fabrication process of semiconductor integrated circuits, a conductor layer of a submicron width can be produced with high accuracy.
In conventional semiconductor integrated circuits, their lateral dimensions have thus been reduced markedly but vertical dimensions, such as the film thickness, could not have much been decreased for the following reasons:
(1) Since wiring resistance and parasitic capacitance must be minimized so as to achieve the high operating speed of the device, the thicknesses of a conductor layer and an insulating layer cannot be made so small.
(2) The ion implantation process is indispensable as an impurity introduction technique suitable for miniaturized devices, but if the conductor layer or insulating layer for use as a mask for ion implantation is formed too thin, then its masking effect is lost; this imposes limitations on thinning of these layers.
(3) A decrease in the thickness of the conductor layer or insulating layer often causes an increase in the number of pinholes and deterioration of the film quality, resulting in lowered yield rate of device fabrication and lowered reliability of product devices.
Since the vertical dimensions cannot be reduced so much as the lateral ones for the abovesaid reasons, what is called a step height tends to increase relatively, thus presenting such problems as follows:
First, when the conductor layer or insulating layer is subjected to patterning through dry etching technology featuring anisotropic etching, the side wall of the layer becomes vertical. This debases the coverage of a film formed on the layer to cause shorting between interconnection lines or breakage of them, resulting in appreciably lowered yield of device fabrication. To avoid this, it is necessary to increase the thickness of the film which is formed on the conductor or insulating layer. By the way, in the case of employing the dry etching technology, the ratio in etching rate between a resist material and a material to be etched cannot be set large. Therefore, the resist layer is reduced in thickness during etching. Accordingly, When the film thickness of the material to be etched is large, the resist layer has to be formed to a thickness large enough to serve as an etching mask. However, since an increase in the thickness of the resist layer lowers resolution of a resist pattern which is formed through using lithography minimum dimensions of the pattern that can be obtained become larger as the number of layers increases. In the case of wet etching technology, the layer to be etched is subject to side etching, so that if the layer is thick, the minimum pattern dimension as well as the film thickness inevitably increase as the uppermost layer is approached. This means that even if a multilayer structure is employed to increase the number of layers, the structure cannot be made so high-density, resulting in no particular effect being produced by the multilayer construction. In addition, differences in surface level in respective layers of the multilayer structure are accumulated, and this also imposes limitations on the number of layers constituting the multilayer structure.
Second, photolithography is much affected by unevenness of the specimen surface. The thickness of the resist layer formed on the specimen surface is large on a depression in the specimen surface and small on a projection. Accordingly, when the resist layer patterned under the same exposure condition over the entire area of the surface of the resist layer, the pattern dimension on the projection in the specimen surface becomes smaller than the pattern dimension on the depression.
To solve such problems, there have heretofore been developed various techniques intended for planarizing the surface of each layer of semiconductor integrated circuits. For instance, a selective oxidation technique has been employed for forming a field oxide film that is used for field isolation. This method achieves planarization to some extent (see J. A. Apples et al., "Local Oxidation of Silicon", Philips Res. Repts 25, 118-132, 1970). However, a close examination of the layer surface planarized by this method reveals that the surface is not always flat and contains a lateral extension of the oxide projection called a bird's beak and dump called a bird's head. And this local oxidation of silicon necessitates the use of thermal oxidation that involves high-temperature, long-time heat treatment.
Another planarization technique heretofore developed is a glass flow technique, which is also widely employed (see A. C. Adams et al., "Planarization of Phosphorus-Doped Silicon Dioxide", J. Electrochem. Soc., Vol. 128, No. 2, P 423, 1981). This is a method that forms PSG SiO.sub.2 on a stepped portion and heat treating it by a high temperature annealing process at 900.degree. to 1000.degree. C., thereby changing the stepped portion into a gentle shape. With this method, however, the absolute step height between adjacent layers remains substantially unchanged. By tapering of the stepped portion the coverage of an overlying film is improved but the absolute step height remains unchanged; therefore, the defect of the lithographic technique that is susceptible to the influence of unevenness in the specimen surface is still left unsolved.
For a multilevel metallization structure there have heretofore been reported such planarization techniques as an aluminum anodic process, a lift-off process and resin coating process (see G. C. Schwartz and V. Platter, "An Anodic Process for Forming Planar Interconnection Metallization for Mutilevel LSI", J. Electrochem. Soc., Vol. 122, No. 11, p 1508, Nov. 1975). According to the aluminum anodic process, aluminum is deposited all over the surface of the underlying layer to be deposited upon and then selectively changed by an anodization method into Al.sub.2 O.sub.3 at those areas unnecessary for wiring, thereby to planarize the surface of the aluminum layer. This process enables the multilayer construction and prevents electromigration, but has the defect that high packing density is limited because the wiring pattern has to be designed taking anodic oxidation into account.
The lift-off process is divided into a method of forming conductor wiring layers and then burying an insulating layer between the wiring layers, and a method of forming insulating layers locally and then burying a conductor wiring layer between the insulating layers (see B. M. Welch et al., "LSI Processing Technology for Planar GaAs Integrated Circuits", IEEE Trans.Electron Devices, Vol. ED-27, No. 6, PP 1116-1124, June 1980). To facilitate the lift-off process, it is necessary that the film be formed at low temperatures at which photoresist is not subject to appreciable deformation and deterioration. In general, however, the film formed at low temperatures is poor in quality and is not fit for practical use. The films which can be formed at low temperatures and are fit for practical use a only aluminum and molybdenum. Furthermore, in the conventional semiconductor integrated circuit structure, the underlying layer is uneven, and the thickness of the resist layer and the shape of its side wall differ according to location; therefore, it is difficult to carry out the lift-off over the entire area of the resist layer with good yield. Hence, the lift-off process is not employed in general. The planarization by the resin coating process is effected, for instance, by polyimide resin coating, but this planarization is not satisfactory, either.